The present invention refers to an arrangement for branching, to outgoing information flow branches, an incoming information flow of digital words which are used in a stored program controlled telecommunication system. The words are divided into groups of bits and generated by means of a first information flow generator at a rate which is obtained by means of clock pulses transmitted from a clock pulse source, which information flow is transferred between memory means whose activation inputs are controlled by the clock pulses such that successively arranged memory means in the transfer direction are activated simultaneously to receive successive information included in respective flow. Such an information transfer principle is generally known, for example from an article "Large Scale Systems Architectures" by J. R. Douglas, which in a "Report 23" was published in 1975 by Infotech, England, and which is called a "pipeline" principle.
If, for example, a read-only-random-access-memory is run according to such pipeline principle, such memory comprising an address hold to register one address at a time, a number of addressable memory element groups to store digital words and a word register to hold a word which is read from the memory element groups by means of the associated address, the following state is obtained shortly before one of the clock pulses activates the activation inputs of the address register and the word register: An incoming address waits at the information input of the address register. The address register stores that address which just before the first previous clock pulse had waited at the information input. The address then in the address register has activated the associated memory element group for reading so that the associated digital word waits at the information input of the word register. The word register stores the word which has been read in response to such previous clock pulse. The registered word activates the information output of the word register. By means of each clock pulse, according to the pipeline principle, a new address is "pumped" into the address register and a new read word is "pumped" into the word register. Each processing of a unit of information (according to the example an address flow causing a word flow) included in an information flow, is carried out between two storage means successively arranged in the transfer direction (the address register and the word register according to the present embodiment) and controlled by means of the clock pulse source, requires one period between two successive clock pulses. Such a timing period is needed also if the flow processing only comprises a transfer of an otherwise unit of information from the one to the other memory means.
When processing digital information by means of a computer which controls for example a telecommunication system, both this branching of an information flow into a number of flow branches and the information flows resulting from a convergence of a number of flow branches occur. The execution of instructions and arithmetic operations can be mentioned as examples of flow branching and flow converging respectively. The present invention, however, only treats flow branchings by means of "pipeline" organized memory means. The clock pulse frequency is determined with regard to the transit times of the conductors and to the reaction times of the memory means and interarranged information processing devices, so that the information will be reliably "pumped" through the flow branches of the stored program controlled system. An effective "pipeline" control demands a computer in which the flow speed, the length of the information words (i.e. the number of bits in the digital words) and the branching structure are well adjusted to each other.
It is known, when performing an instruction sequence which is read from an instruction memory, to divide each instruction word into an operation field, a format field and a variable field. By decoding the operation field direct orders are obtained as to how the variable field shall be used, one or several flow branches being allocated besides the decoder branch. If the pipeline principle is used each information processing between two pipeline activation points requres one timing period, as has been described already. Accordingly, there is no profit utilizing long instruction words containing lots of information, which are read from the instruction memory one per timing period, if the branching process then uses up more than one period during which the successive instruction is not allowed to be transferred to the branching arrangement. It is known to solve such data processing problems either by having an overlap upon the performance of successively read instructions or parts of an instruction (if the control process itself allows such overlap) or by buffer-storing result information (if the control process does not allow an immediate overlap). The mentioned problem in connection with the use of the pipeline principle is treated by J. Sell in an article "Microprogramming in the Hewlett-Packard 3000", which also is part of said Infotech-Report 23. This article also describes a branching technique in connection with instruction performance, which is based upon two successively arranged instruction word registers according to the pipeline principle.